In helping to establish the protocol being used this info from the datasheet may be useful. The BCM and MCM also have RS485 chips on board which are being driven by these serial channels on the CPU.
Page 417 & 418 also look useful in the datasheet.
H8/538 CPU Section 14 Serial Communication Interface
14.1 Overview
The on-chip serial communication interface (SCI) Note the naming convention here that matches our BATTSCI & METSCI wires in manual. has two independent channels in the H8/538, and three independent channels in the H8/539. All channels are functionally identical. The SCI supports both asynchronous and clocked synchronous serial communication. It also has a multiprocessor communication function for serial communication among two or more processors. The H8/538 does not have SCI3.
14.1.1 Features
SCI features are listed below.
• Selection of asynchronous or synchronous mode
a. Asynchronous mode
The SCI can communicate with a UART (universal asynchronous receiver/transmitter),
ACIA (asynchronous communication interface adapter), or other chip that employs
standard asynchronous serial communication. It can also communicate with two or more
other processors using the multiprocessor communication function.
There are twelve selectable serial data communication formats.
— Data length: seven or eight bits
— Stop bit length: one or two bits
— Parity: even, odd, or none
— Multiprocessor bit: one or none
— Receive error detection: parity, overrun, and framing errors
— Break detection: by reading the RXD level directly when a framing error occurs
b. Clocked synchronous mode
Serial data communication is synchronized with a clock signal. The SCI can
communicate with other chips having a clocked synchronous communication function.
— Data length: eight bits
— Receive error detection: overrun errors
• Full duplex communication
The transmitting and receiving sections are independent, so the SCI can transmit and receive
simultaneously. Both sections use double buffering, so continuous data transfer is possible in
both the transmit and receive directions.
389
• Built-in baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: baud rate generator or SCK pin
• Four types of interrupts
Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are
requested independently. The transmit-data-empty and receive-data-full interrupts can be
served by the on-chip data transfer controller (DTC) to transfer data.
In the H8/539, SCI2 and SCI3 have the same interrupt vectors.
Last edited by retepsnikrep; 03-14-2009 at 01:38 PM.
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